Full-Custom Design Services
A full-stack offering for full-custom physical design, creating a highly-optimized, fine-tuned circuit, laid out transistor by transistor for maximum performance.
The Full-Stack of Full-Custom Design
Our customers could do it themselves — many have very capable and experienced teams of their own.
But they might not want to hire a full digital team and have the RTL architect remain idle while layout happens. Or they have a full digital team, but want more expertise in a specific niche of digital design.
The default strategy for leading-node digital teams is to raise half a billion dollars to deliver a product. DXCorr provides a better solution. By augmenting your in-house team with our experts, DXCorr can ensure that your tape out happens with a fraction of that price.
Front End
RTL design & design verification
Process migration and cost reduction
Physical IP selection and trade-Off analysis
Logic synthesis
DfT insertion and verification
chip partitioning
Back End
Floorplanning
Clock and power planning
Timing constraints generation
Place-and-route and timing closure
Clock tree synthesis
Chip Finishing
Chip finishing and quality control
IR drop and EM analysis
Routing and signal integrity closure
Sign-off extraction and timing and noise verification
Physical verification (LVS, DRC and antenna)
DfM and parametric yield improvement
full chip tape-out
Philosophy
We bring the same bold philosophy behind the creation of our leading physical IP to our customers’ specific needs with our full-custom design services.
DXCorr has experience with bleeding-edge technologies that most physical design firms don’t touch, such as new materials (MRAM), new kinds of transistor (such as our nanowire SRAM research), custom DRC waivers, and near-threshold design for voltages of as low as 0.28V. Even for customers who innovate at the polygon level and demand only the best performance physically possible, DXCorr can provide custom solutions. In fact, many major semiconductor companies with substantial in-house physical design teams still choose to use DXCorr’s expertise to augment their own.
Track Record
As a digital architect at Sun Microsystems, for years, our CTO Sagar was often tasked with delivering specs that were conventionally impossible, and developed a fundamental appreciation for the experience required to do so while keeping tapeouts on time. Having learned what to look for, Sagar has hired a team that brings centuries of experience working with the latest foundry technologies, the most unconventional design tricks, and the most unusual product constraints.
That’s why DXCorr has never missed our stated deadlines for a single tapeout. We’ve completed dozens of tapeouts for our customers in addition to our dozens of physical IP blocks, from ultra-low-leakage glitchless adders for Audi, to foundation IP for major foundries like GlobalFoundries. We’ve done it all without missing a beat, because none of our customers can afford to wait.